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Recent content by ananth_anbu

  1. ananth_anbu

    FPGA <-> SATA disk?

    serial ata fpga Hi All, I am working PCI Express design in our project. I am using the GTP core which is existing the Pci end point interface design is connected diff clock interface. We are not yet recevie the clk properly. The ref clock we are using to generate the core is 100Mhz , 4...
  2. ananth_anbu

    files needed for timing simulation

    Hi, u can find solution for doubts on xilinx website. They provides all the details about tool,STA,synthesis issues.Go and search www.xilinx.com bye
  3. ananth_anbu

    Wnat to know about certificate coursess

    Hi all, I am a BE Graduate. Currently i am working in networking field - 2 yrs. Now i want to do networking course. In networking, which coursess will give great job opertunity in MNCs. Ple... Thank u
  4. ananth_anbu

    What is the inter and intra delay in Verilog?

    verilog question Hi, what is inter delay and intra deay in verilog? ple explain?
  5. ananth_anbu

    C Based Verification in VLSI

    Hi, i need the details about C Based verfication in VLSI. I have knowledge about PLI (Programming Language Interface). I Expect More about Real Time Methods in this case. Kindly show me any answer or files for me
  6. ananth_anbu

    How does setup time impose maximum delay and hold time the minimum delay?

    hi, i have doubt in setup and hold time. Setup time imposes a maximum delay requirement, Hold time imposes a minimum delay requirement. How? ple. explain me
  7. ananth_anbu

    the way to generate register

    Hi ur answer helpful me too . ple tell me how to instantiate the vendors RAM in the device directly?

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