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$monitor & $display in verilog
Haiii ,
$display and $strobe display once every time they are executed, where as $monitor displays every time one of its parameters changes.
The difference between $display and $strobe is that $strobe displays the parameters at the very end of the current...
haiii ,
I have some ideas on this.
the Setup time margin is:
( Tclk - (Tclk-q + T combn + T clkskew) - T su >= 0
the Hold time margin is:
Tclk-q + T combn - T clkskew - T hold >= 0
If both the margins are not satisfied (ie. it becomes -ve), then the setup time and hold time...
wire load models
haiii,
how does the WLM plays a role in Timing calculation????
If we change the WLM for a synthesis , then the timing calculations will differe or not???
Re: Verilog or VHDL
Haiii all,
Let me join the discussion of VHDL Vs Verilog.
So far I have involved in two FPGA & one ASIC designs (front end)
Have a look at the attached document for table of differences.
Re: Gate level net list
Haii miho,
If this is the case , we can get timing details from the physical synthesis unlike logical synthesis.
how far that results reflect the final stage timing closure???
how does the SPEF file generated???[/code]
haii ,
I already seen more websites for the formulaes.
also there are lot of variants in the formulaes such as:
Hold time <= Σ shorest contamination path delays
<= propagation delay
<= clk-Q delay + combinational path delay - clk skew
Setup time...
Re: a doubt in verilog
Haii ,
I got the following error in Xilinx ISE 6.1.03i , while i have synthesized the code from Mr.nand gates,
As we are checking the negedge of the RESET in the event list where the "q" is resettted for RESET =1, the condition got failed.
Is it the error due to...
Haiii all,
On summary , it is just like as:
Design Entry (HDL code) ---> Simulation (Functional ) -----> Synthesis (Logical or Physical) -----> P&R--->Gate level Functional & Timing verification ---> RTL changes(optional) Back Annotation----> Tapeout.
Correct me if any wrong
Re: Setup & Holdtime
Haiii,
I think SETUP and HOLD time are of same meaning for FF & Latch in the sense of their requirements, only thing that differs is the EDGE or LEVEL for sampling or latching.
But the values of SETUP and HOLD time for FF and Latch in a particular technology may differ...
Re: Gate level net list
Haii omara,
thanks for the detailed explaination on delays.
But as SMITH said , if the logical synthesis is giving way to physical synthesis, then we can get the timing information even after "synthesis" in the netlist itself?????
Re: Gate level net list
Haiii reddy,
I have gone thru ur replies so far.
If the Interconnect delay is not so accurate in the gate level netlist (technology dependent), then how the accuracy of the Component delay ???
If a technology mapping happens, then definitely the delays incurred...
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