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Why is no load worst case for stability analysis of opamp?
What happens if we have load resistance and do stability analysis? ( ie break loop and test)
Why should we have load capacitance while doing stability analysis?
Why should we not have load resistance while doing stability analysis?
What do you mean by noise pulse processing compensation?
is the audio signal delayed until noise gate does it work ?
---------- Post added at 13:22 ---------- Previous post was at 13:18 ----------
@FvM, Do you mean that noise events get triggered? Please explain? I will do analog design...
how to achieve faster attack time on audio noise gate circuit
Hi,
In audio noise gate circuit design , how to achieve faster attack time?
What does the noise gate circuit look like? How can we do it in IC design?
In other words if the audio input signal is say less than 1mvpeak, we should...
How will it be unity gain in DC? In DC capacitor is open and then dc gain is (1+ R1/R2) ? Am I wrong?
---------- Post added at 15:18 ---------- Previous post was at 15:07 ----------
Sorry i missed the point that R2 and C2 are in series. looks like the capacitor value is large which means large...
the input signal is in the audio frequency range. Settling time is max 1millisec. How can I have two subcircuits? AC or small signal 100mv should ride on dc 1.8v.
Thanks.
in ADE go to OUTPUTS -> TO BE PLOTTED -> SELECT ON SCHEMATIC, then click on the terminal to be plotted ( Red hollow square)
After running the simulation, you should get the current of that node vs frequency.
Hi I would like to get circuit ideas for the following:
Dc gain = 1 (unity gain)
Ac gain = 100
That is if I give 1.8v DC + 1mV sine signal , the output should be 1.8v DC + 100mV sine signal. The output response should be fast ( fast settlinfg time)
Hi,
My OTA in the attached figure is unstable. I would like to know where to add compensation capacitor, so that it becomes stable. each OTA by itself is stable.
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