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Recent content by analayout

  1. A

    Core device orientation in 28 nm

    I heard it is some thing related to wavelength of the light source used in photolithography.
  2. A

    Core device orientation in 28 nm

    Hi All, In 28 nm process the core device should be placed in same orientation. Why is it required ? regards, Analayout
  3. A

    Dongbu - pdk installation issue

    Hi, I have to setup the following pdk .35um 85v Dongbu kit. I have downloaded the kit from their site. But the issue is there are no standard cell libraries , IO_cell libraries along with the pdk. Any idea where can i get these standard cells and IO libraries ? Also the pdk is for cadence IC...
  4. A

    EDA suitable tools for the educational and research purpose....

    Hi Junus, For fabrication and EDA set up and other IC design related consultancy service you can contact wafercat from SAudi Arabia. Their website is www.wafercat.com , they have very good deals for academic institutions. Regards, Analayout.
  5. A

    What is the future for CMOS Analog IC Designers ?

    Hi, What about layout guys!!!!! Regards,
  6. A

    N-type and P-type antenna diodes roles

    how bise a transistor hi, erikil wrote Not, if it's a p+diode in n-well, and n-well is biased by vdd ! Cheers, erikl if its n+ diode in Nwell then its not allowed. so my point is the diode should be reverse biased. its better to put in substate than in nwell. because this will cause...
  7. A

    N-type and P-type antenna diodes roles

    antenna effect,plasma induced damage,layout Hi, I think we can put only n+ diode only. if we put p+ then it is same as the gate is connected to substrate. Regards, Analayout.
  8. A

    Diffusion area in MOS

    Hi, colin and the last guy are correct. first the poly will be fabricated then with the rectangle mask source and drain will be fabricated . This time the poly will act as a mask under poly there will not be any diffusion formed. You can get the fabrication step in google there you will...
  9. A

    Regarding Via in layout

    Hi, Via 1 -> which conncts M1 to M2 Via 2 -> which connects M2 to M3 Via3 -> which connects M3 to M4 and so on. One via which named as CO which will connect M1 -> poly or M1 -> OD depends on which layer is below the M1 Regards, Analayout.
  10. A

    Help me solve 555 timer equations

    555 equations Hi, You can just look at the block diagram of 555 timer then you will get an idea. you can get BD from internet Regards, Analayout.
  11. A

    Why Shielding lines are connected to VSS not to VDD

    speed sensor connect how to signal Hi , Is emi shielding and electro static shielding are same ? Wht i meant is shielding in high freequeny Ic layout eg:- shielding of Differential pair input in ADC layout. Regards, Analayout.
  12. A

    Why Shielding lines are connected to VSS not to VDD

    shielding of analog signals Hi All, Why Generally shielding lines are connected to VSS not to VDD ? Regards, Analayout.
  13. A

    Covering the poly routing with implant layers

    Re: Poly layer Route Hii, WHich pdk you are uding ?
  14. A

    spacing between N+ diffusion and NWELL

    Hi , There is some explanation about this in the following book. Art of Analog Layout by Alan Hastings 2nd Edition p. No . 518 Diffusion near the Channell . I think you will get some idea from there. Regards, Analayout.
  15. A

    spacing between N+ diffusion and NWELL

    Hi, I think it has some relation with WPE effect Regards, Analayout.
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