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Recent content by AmrZohny

  1. A

    Sigma Delta Modulator Simulation

    try **broken link removed** and get hands-on experience with this https://www.mathworks.com/matlabcentral/fileexchange/2460-sd-toolbox
  2. A

    Transmission gate D-flip flop simulation issue

    https://cmosedu.com/cmos1/book.htm with video lectures and assignment solutions Cheers
  3. A

    In phase and quadrature components of a sine wave and a cosine wave

    Later it depends then on your channel modulation technique... You can code in three levels ( i.e -1,0,1) or 2 levels or M-levels ... but in general yeah ...your demodulated I and Q signals would follow simply as such - - - Updated - - - Basically so ...
  4. A

    Sigma Delta Modulator Simulation

    Along with the simulink model **broken link removed** hope it helps Cheers
  5. A

    Transmission gate D-flip flop simulation issue

    I recommended it since I do not know how big a load viperpaki007 is driving....its advantage is the ability to cascade tapered inverters to be able to drive big loads at the end ...
  6. A

    Matlab Learning tutorial and study Material

    https://www.mathworks.de/academia/student_center/tutorials/launchpad.html Cheers mate
  7. A

    Transmission gate D-flip flop simulation issue

    I think this is what FvM means ... but you still have to use a NOCG circuit to drive the T-gates https://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/40-cmos/dff.html
  8. A

    Transmission gate D-flip flop simulation issue

    You can't drive a T-gate with such an arrangement for clock generation...The way you got it, you are loading the CLOCK_POS more than CLOCK_NEG since it is extra loaded with the inverter producing CLOCK_NEG itself ... you have to use a non-overlapping clock generation circuit like this one...
  9. A

    The best layout design and simulation software [hlp]

    Cheers mate https://www.linear.com/designtools/software/
  10. A

    Rise time and frequency scaling

    Rise time is a function in both Ron of the transistor as well as CL As the technology scales, the parasitic capacitance of the inverter (basic digital block for eg.) goes down. **broken link removed** However, the on-resistance does not scale on the same ladder.... RON = 1/(µnCOX W/L)(VGS −...
  11. A

    Transmission gate D-flip flop simulation issue

    Can you show me the simulation of the signals CLOCK_POS and CLOCK NEG You get the problem on CLOCK edge ... therefore I think there might be something with your non-overlapping clock generator ....
  12. A

    how transistor work in unlinear statues and as demodulator

    This is a good guide https://csus-dspace.calstate.edu/bitstream/handle/10211.9/1419/Final_Report.pdf?sequence=3 hope it helps
  13. A

    how transistor work in unlinear statues and as demodulator

    https://edn.com/design/other/4312213/Three-transistor-modulator-amplifier-circuit-works-with-swept-control-frequencies **broken link removed** Cheers...
  14. A

    how to transform frequency domain data to time domain data

    Your answer is here = ) **broken link removed**
  15. A

    How to change 3 ports s-parameter to Reflection coefficient

    For port 1 it is S11 For port 2 it is S22 and for port 3 it is S33 ! Or did I wrongfully understand the question ?
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