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Thanks Rahul.
Unfortunately, I already know the basic of characterization with Liberty files which you are mentioning above.
What I really do want is the mathematical interpolation expression for 3-D lookup table.
Ex.
D0 = (tr20*c20)*D11 + (tr20*c01)*D12 + (tr01*c20)*D21 + (tr01*c01)*D22
where...
Anybody knows how to interpolate delay values from the 3-D lookup table in the Liberty file?
here are some sample template:
/* 3-D table template f(i_trans, o_cap, r_cap) */
lu_table_template( f_itrans_ocap_rcap ) {
variable_1 : input_net_transition;
variable_2 ...
Yeah right, well said.
That's why before wasting too much time and effort, I looked for consultation in this site. :-)
Actually, I am involved in FPGA design in the HW IP level not on the board level.
Currently, we don't have methodology yet for Full-chip timing analysis.
And I think based on...
Thanks ads-ee. :grin:
Yes, you've correctly pointed-out the real problem with characterizing routing IPs in the first part of your reply and that's where I'm looking for help.
And also yes, this was originally posted in ASIC Design Methodologies forum but was moved by admin. You're correct that...
[STA] FPGA ROUTING block representation for top-level STA
Hi, anybody here doing IP characterization for FPGA? I just wonder how do you represent ROUTING block for top-level STA.
I am doing top-level STA using FPGA IPs but to correctly represent the actual FPGA setup, I need not just IP block...
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