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please specify how configuration register will be used for clock control?
what i understand is is some count value can be configured and can be used for clock division or so.
what are other scenarios.
please let me know,
1.in AHB why do we use lock signal.
2.what happens if select signal is deasserted as the transaction is finished,but lock signal is still active?
Thank you in advance.
uart controller using verilog
advanced digital design with the verilog hdl micheal d. ciletti has synthesizable model with netlist explanation go for that buk
in the first case
1. signal = latch , + = half adder, out = wire
so latch ,adder = wire out
2. input = wire , output = wire, half adder
this will be the difference.its better yu synthesize and check as the signal might be taken as an FF too.
thank you
Re: Clock domain Crossing
In a circuit where an asynchronous signal has to be synchronised with the clk,the MTBF comes into picture.
MTBF = 1/(Fclk * Fin *Td)
Td = critical time window(the addition of setup time and hold time)
so different synchroniser ckts can...
Re: AMBA question
A conventional interleaved memory provides an "even" memory bank and an "odd" memory bank. Data having even memory addresses are stored in the even memory bank. Data having odd memory addresses are stored in the odd memory bank. Hence, any two sequential memory locations are...
what is elaborte in ncsim
During compilation,the individual source files are compiled into libraries and translated to object code. During elaboration, a top-level unit is selected and,
using the configuration information, a hierarchical model is built by
recursively connecting entities and...
when p and n are interchanged?
1.P -strong '1', weak '0' reason -not complete discharge of output capacitance load thereby weak '0'.(derived from vdd equations)
n - stron '0' , weak '1' reason - not complete charging of output capacitance load thereby weak '1'.
so when...
Re: CMOS inverter
when p and n are interchanged?
1.P -strong '1', weak '0' reason -not complete discharge of output capacitance load thereby weak '0'.(derived from vdd equations)
n - stron '0' , weak '1' reason - not complete charging of output capacitance load thereby weak '1'.
so when...
Re: about ahb decoder
A central address decoder is used to provide a select signal, HSELx, for each slave on the bus.The select signal is a combinatorial decode of the high-order address signals.the decoder design is based upon the number of slaves present and not upon the master.
u can get a...
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