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Hi
I don't know what simulation software you are using, if you are using cadence then in cadence documentation you will get all the details of how to simulate an LNA in cadence.
Hi all,
I am working on single electronics.I have designed a macro model of a single electron transistor(SET) in T-spice.But when I am trying to use it in a circuit by including its macro model file to analyze its characteristics the simulation results showing an error "Missing Switch model...
Thanks for the reply.Actually I am not creating the lay out of the mos by putting layer over layer, what I am doing is I am using the option gen from source in lay out editor by which I am getting the lay out view of the NMOS transistors and all other components,which I am just connecting...
Hi all,
I am using umc 0.18um RF/Mixedmode CMOS technology in my project.I have used three terminal inductor,capacitor,resistor and four terminal NMOS in my design.after designing the schematic I have used the gen from source option to create the layout of different component.after that I have...
hi,siva
actually I have faced the same problem that u have described here,and I have tried to solve this in that way but the problem is I could not find that lay_cap_ground file. so it would be really helpful if u can tell me where I will get that file.
thanks
amit
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