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Thanks for the advice. I changed my actual code and used non-blocking assignments to clear the registers in the else statement.
I can't use non-blocking in the (if) part because I need it to execute sequentially.
I have this for loop in my actual code in the if part to initialize SR_temp, is...
Sorry for the late response, but when I was writing an example code, I noticed I was reading out the value at the same time of calculating the new desired value, so I solved the problem by postponing the read until the next CLK. Now when synthesizing the code I get the following warning about...
Thanks for your reply. I cant put my code it's very large and complicated.
I put a break-point inside the generate for loop and noticed that for different genvar value the statements inside the generate loop are executed in different times, (i.e when i = 0 the time is 135ns and when i =1 the...
Salam everyone,
I'm new to the forum, I'll try to explain my problem step by step:
In my verilog code I have one top module and one sub module that is generated many times using generate for loop, the output of one sub-module is an input to the next,
These I/Os is declared as array of wires in...
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