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Recent content by amarnath

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    What are the circuit techniques to improve LDO's PSRR in higher frequencies?

    Re: LDO's PSRR PSRR is a function of the loop gain (Aopenloop*Beta). So it can be maximized by increasing loop gain.
  2. A

    low drop out voltage regulator

    Just search for middlebrook's method. Connect a very big inductor from the feedback node back to your opamp input (its a dc short and ac open circuit) . add an ac voltage source to your input 1 v AC and run ac analysis by sweeping the frequency. observe the gain and phase plots and let me know...
  3. A

    The curvature of my BGR output is wrong. Why?

    I think your ctat component is more inherently. What correction are you trying to do ? is it second order? Amarnath
  4. A

    About Charge Pump and VCO

    http://www.geocities.com/fudinggepll/index.html http://www.geocities.com/fudinggepll/PLLProj.pdf First link takes you to the page , the second is the link to the document on PLL's which i think is very good. amarnath
  5. A

    Why for Charge Pump they do Phase Noise analysis??

    You do it so that you can asess how much of the phase noise is contributed by the charge pump to the output clock. amarnath
  6. A

    How to select charge pump current?

    Yes i understand, thats why i said it all depends on what application the PLL is going to be put to use to. For lower end applications it may not matter as much, but it is good to understand what each parameter does before choosing a value for the same for whatever application it may be. amarnath
  7. A

    charge pump applications with explanation

    charge pump which charge pump do you mean a voltage charge pump to pump up the voltage or the one used in PLL's/ amarnath
  8. A

    How to select charge pump current?

    choosing a charge pump current wn=sqrt(ip*kvco)/(2*pi*N*C1).Fit in the other parameters like divider ratio, gain of the VCO and the loop filter capacitor. Overall the pump current is chosen based on noise requiremtns ,BW,lock time etc.You can refer to the book PLL frequency synthesizers by...
  9. A

    ring oscillator frequency variation

    yes you need to use trimming to trim the frequency across corners. But variation across V-T can also be high enough, but atleast you can remove the variation across process by having sufficient trimming. amarnath
  10. A

    About Charge Pump and VCO

    Hi Mouzid, please do a google search for "Fuding Ge pll thesis" There you will get this thesis. Yes the loop filter needs to be designed so that the PLL locks to the input frequencies.You will find the standard design equations in any design book. Amarnath
  11. A

    Reducing ripples in VCO

    to reduce the ripple on the control voltage size the capacitor to filter the ripple.In a second order loop filter the second pole should be sized to filter out the ripple.
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    DLL based Frequency Multiplier for PCS application

    He means , he is going to generate multiple phases and then using these phase he could double or quadruple the input clock frequency. amarnath
  13. A

    static phase offset PLL

    in any feedback system the output settles to some value within some error % difference compared to the input. This error reduces but cannot be eliminated, it is less in case of second order PLL. amarnath
  14. A

    Frequency Compensation

    The resistor nullfies the zero if its sized such that it cancels out the zero created by the miller cap. The resistor can also be sized to move the zero to the right half plane to increase the phase margin. amarnath
  15. A

    Frequency Compensation

    Just add a miller cap as in a two stage opamp, this will introduce a zero since you now create another path for the signal to reach the output.Then try moving this zero to the right half if needed to improve your phase margin. amarnath

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