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Hi,
I want to design for frequency components from very low frequency to 100MHz.
i.e., for any frequency my output should be 1/4 period of that particular frequency component.
Bye.
Hi,
I want to design a circuit which will generate delay of 1/4 of the period.
For example
If i will give the input 100KHz with 0ns delay, my output should be 100KHz with delay of 25KHz.
Please any one help. It is very urgent.
Bye
how to measure dnl
Hello,
I have designed 8-bit pipelined ADC wants to measure INL and DNL in spectre or smartspice . Please any one help me in finding INL and DNL . If any scripts is there provide me.
transistor dac
Hai ,
Iam fresher in design please help me with some doucment for DAC resistive and current steering dac so that it will help me . please mail me to this id amahi07@gmail.com .
Bye .
According to me . We check for four corners , FF , SS , SF, FS . Since TOX is not uniform through out die . So our circuit should work at any place of die . we check our circuit parameters at all corners like Fast , Slow and Typical .
Regarding Multi fingers to have better matching. and uniform...
Please help in providing some Document for current or resistive DAC .
Iam facing some problem in settling time , INL , DNL .
My DNL range is -1 to 1
My INL range is -1.5 to 1.5
But Iam getting very large INL , but DNL is not giving any problem .
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