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Recent content by Alvin80

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    Formality: problem with design including clock-gating

    clock gating + formality I suppose that my low-power optimization of the design can change something in the circuit and so the waveform of some signals will be different w.r.t. the original design. However, the changes don't have to affect the behaviour of the entire circuit and so the output...
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    Formality: problem with design including clock-gating

    formality clock gating Hi everybody, I'm a newbie of Formality tool environment. I applied my own clock-gating technique on a design and I would like to validate that the optimization doesn't corrupt the behaviour of the design. Functional verification passed usign NCSIM. Formal verification...
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    Problem: simulation RTL --> vcd file (using NCSIM)

    vhdl code shm output Solution found!!! The problem was the NCSIM version. I was using NCSIM 5.70 ... now I'm using NCSIM 8.1 and I don't have any troubles if I use this simulation flow : - After ncvlog, ncelab... ncsim +access+rwc -MESSAGES -CDSLIB cds.lib -LOG ../log/ncsim.log -BATCH...
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    Problem: simulation RTL --> vcd file (using NCSIM)

    dump vcd file simulation Useful suggest!! But I still have a problem. I can dump a vcd file, but I find a vector format of the registers bank in my design. Example: $var wire 28 x! x_reg_bank[9] $end $var wire 28 y! x_reg_bank[8] $end $var wire 28 z! x_reg_bank[7] $end $var wire 28 {...
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    read_saif command - help needed

    Re: read_saif command help I think that the best tool for power estimation is Power Compiler, but if you also need to do static timing analysis, you can easily use PrimeTime and the command "report_power -cell_power". This command print the report power of all the cell in the $current_instance...
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    Problem: simulation RTL --> vcd file (using NCSIM)

    ncsim vcd Thanks for the answer... But I need to create a SAIF file and I cannot modify the RTL code (no DPFLI function or other pragma can be introduced). I know how I can translate vcd to SAIF....but I don't know how to create a SAIF from a shm database. How can you create a SAIF file after a...
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    read_saif command - help needed

    Re: read_saif command help Using Synopsys Power Compiler 2006.06, after reading the SAIF file, you need to use the command "report_power -instance $block1 > $OUTPUT_DIR/$block1.power.rpt" and "report_power -instance $block2 > $OUTPUT_DIR/$block2.power.rpt" Obviously the design has to be...
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    read_saif command - help needed

    Re: read_saif command help You can annotate the activity of all the design and then you can do "report_power" only for the desired blocks. I think that is more correct for evaluating power of a design.
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    Problem: simulation RTL --> vcd file (using NCSIM)

    ncsim probe -create -shm Hi everybody, I'm working with NCSIM for simulating a hierarchical design at RT-level. I'm especially interested in the activity of some register banks in the design. Thus, I prepared the following script in order to annotate this activity into a vcd file. cat >...
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