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how much reverse-bias current is safe ? we can not find this parameter from transistor datasheet.
from fig,Iec=(enlargement factor)*Ieb ?
if i use following sch,does it work well?
thanks you.
maybe i can try to use a 2:1 circuit to divide ADC output into half,from 20MHz data divid into 10MHz.it will give me more time to take care of delay.
thank laktronics
your suggest is another method, if I use this method: use still 20MHz clock to AD converter,then use prescale clock to address counter.because i need about 12 type sample rate:10M,5M,2.5M,1.25M ...,so i need a mux to select difference clock to address counter,the counter will...
I can not only use prescaler to AD converter clock,because ad converter can not work below 20MHz,so I need maintain ad converter clock >20Mhz,such as 100MHz,then use prescaler to generate slow clock for sram.
I design a digital oscilloscope,use a 100MHz AD converter ADC08100,ADC08100 can not work below 20MHz sample rate.
but i need slow sample rate,such as 5MHz,1MHz,200KHz.......So I think use 100Mhz clock to sample,and use slow clock(ex.5MHz)
to store sram,equal every 5 sample only store one data...
many oscilloscope have random sample function,example:100MHz real sample oscilloscope ca realize 5G random sample rate.
how to realize random sample? anyone can help me?
jyetech oscilloscope source code
random repetitive sample can reach high sample rate(ex.5GHZ) use low sample adc(ex.100MHZ),but how to realize random repetitive sample?
tdc time
I want build a TDC circuit for my oscilloscope random repetitive sample,use TDC circuit to measure time between trig point to first sample clock .I select anlog TDC circuit,when trig occur,start current source fast charge capcitance, and first sample clk to stop slow discharge...
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