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Recent content by alpeshchokshi

  1. A

    Regarding reusing a checker in the system level

    Re: regarding checker you can use it... you need to make your IO ports compatible to top level interface...
  2. A

    Why we use CMOS even when there is BJT?

    Re: y use CMOS ?? less power consumption, full swing complemetary signals, more bulky but reliable
  3. A

    Issues to be taken care during clock changes

    you can use the double flop synchronizer or fifo based synchronizer
  4. A

    validation of a project means what ?

    validation is done, once the real silicon comes from the fab. The post silicon validation is done of board level and system level.
  5. A

    What is the effect of clock gating in design?

    Re: Clock Gating clk gating is used for power saving... at the same time in DFT its required for testmode and normal mode.
  6. A

    How to do GLS simulation ?

    Re: GLS Simulation please upload the tutorial i badly need it.
  7. A

    do you add propagation delay when doing transition fault tes

    Re: do you add propagation delay when doing transition fault yes we used to add net delay, as well as gate delay
  8. A

    Need description of Verdi shorcuts

    Re: Verdi shorcuts I also need any manual for verdi, if some one can upload it will be a great help!!! thanks,
  9. A

    Spygalss training materials(Need)

    what is spyglass and what are the uses of it??? can somebody please explain me in detail????
  10. A

    Recommend me books about Physical Design

    Re: PD what is the mean of "PD"?
  11. A

    What is a DFT library ?

    Re: what is dft library? Can someone more elaborate on DFT library?? I am the new in this area and dont know much about it......
  12. A

    E as the verification language in comparison with others

    Re: E is the only one? Specman is the environment for language "e" and its from cadence. whereas system verilog is from synopsys. it uses for both design as well as verification purpose. No doubt, more and more people are migrating toward the SV but still e language has its own slot in the...
  13. A

    can you me the recent technologies..where FPGA is employed?

    Re: can you me the recent technologies..where FPGA is employ Mostly it uses for emulation of prototype design in industry
  14. A

    Silicon validation on ASIC

    For silicon validation... there are always.. DFx (Design for *) features added in to the design... It goes with the RTL on die...Once the silicon is ready, this feature are used to test whether the silicon is healthy or not. Interms of functionality, routing, all paths, etc.
  15. A

    Interfacing VHDL design with a Verilog testbench

    its really nice answer....
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