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You just need to use some good solder flux. The surface tension will naturally remove shorts, as long as you don't have too much solder.
The best way is a technique called drag soldering: https://www.youtube.com/watch?v=wUyetZ5RtPs
And here's a longer guide for SMD soldering in general...
Recharacterizing SRAM IP at lower voltage?
I'm using ARM IP's SRAM memory compiler for IBM 130nm. It is only characterized for nominal voltage and some worst case corners. I'd like to scale VDD significantly since I only need a fraction of its specified performance at full voltage. I do have...
I have a layout for series resistors with instance names like:
|R1 |R2 |R3 |R4
In my schematic I have four resistors with the nets inbetween named t0, t1, t2. I have the connectivity of these nets well defined in Layout XL.
I go to Connectivity->Check->Against Source, and it says there are 0...
I'm using cells to create the VDD/VSS power grid. The bottommost cell in the hierarchy is just two metal lines crossing each other with a via. Since there are no instances in the layout or schematic, just wires, LVS fails on this cell:
ERROR: Nothing in source.
ERROR: Nothing in layout.
ERROR...
Everytime I run Calibre for DRC I get around 50000 warnings like this:
Cell name parameter <blah> for INSIDE CELL operation not located.
How do I suppress these warnings?
Thanks. Now I'm trying to use the regular definition of Q as -imag(y11)/real(y11) to get Q at resonance. However, isn't imag(y11) = 0 at resonance? How do you evalulate Q this way?
edit: Nevermind, I figured this out.
I'm calculating 1/(w*imag(y11)) to view inductance. However, using two different equations gets different results at DC:
Red curve: -1/(2*pi*w*imag(Y11)
Blue curve: 1/(2*pi*w) * imag(1/Y11)
Why are they different? The blue one is correct at DC and doesn't have have huge spikes.
I added a clarification that my question is in the context of designing standard cells (ie. transistor level)
Ok, I showed the wrong NAND-based version of a master-slave flip flop. I mean to compare the transmission gate version to the standard version I've seen often in textbooks on digital...
In Baker's book he introduces an edge triggered D flip-flop using transmission gates:
**broken link removed**
However I can't find much information about the advantages and disadvantages of this design compared to the regular NAND implementation. I noticed from simulations that the tgate...
Perhaps rise time doesn't decrease but the dv/dt of the signals has to decrease since the transistors have smaller Vgs - Vth, and larger resistance. However the effect will be minor compared to performance loss from lowering VDD. I'm assuming the question means decreasing VDD for a specific...
Smaller supply voltage means slower rise/fall times which means less crosstalk. There's a graph here: https://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.43.4654&rep=rep1&type=pdf
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