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i have this code in VHDL :
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity nibble_comparator is
port(a,b : in STD_LOGIC_vector(3 downto 0);
gt,eq,lt: in STD_LOGIC;
a_gt_b, a_eq_b, a_lt_b : out STD_LOGIC);
END...
so can you explain what exactly happen when vin1 goes less than vin2 ?
i think it must be like this:
when vin1 >> vin2 :
m2 -> off and and all current will flow through m1 and m3. due to vgs3, m4 can not be off and operate in deep triode. so vout goes high.
but when vin2>>vin1:
m1-> off and...
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