Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
In my rectilinear design there are 10 edges, and each edge is having some number of ports.
I want to get the information of ports interactively which are sitting on each edge .
So, Can anyone please help me with this thing. It will be really helpful for me.
PS: I do not want to select...
Hi,
I agree that Calibre is a signoff tool for DRC.
Just wanted to know what could be the exact reason for using Calibre when ICC itself is checking for DRCs.
Hi,
Can anyone please explain the importance of a generated clock and its advantages.
Can't we have only the master clock in a design without using any generated clock?
Thanks
Hi,
When I checked about the reason why we see "No Constrained paths" or "No Paths" in PrimeTime when we do report_timing -from <start_point> -to <end_point> , I got to know that there might be few reasons which are given below.
There is no topological combinational path between these two...
Hi,
I have a design in which there are few DRCs(eg:50) showing in ReRoute(ICC2 too) log file but calibre DRC count is showing 80.
Can anyone please explain why the DRC count is different and why we are using Calibre as a signoff tool when we have an icc2?
And also please explain about DRC Dec...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.