Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by Ali_louati

  1. A

    [SOLVED] Bit select not declared -VHDL error

    Hi Dpaul, Yes I attached a netlist that I generate from Synopsis design_vision. I don't have the verilog file of this design. I have just the VHDL code. For that reason I attached the VHDL code in the begining. I will try to explain better my problem. I would like to check the coverage of...
  2. A

    [SOLVED] Bit select not declared -VHDL error

    Hi FvM, Thank you for your answer. No it wasn't a mistake. I put the VHDL code because I thought maybe I should change the expression of integer range to another expression. I think When I synthesised the design it give me something wrong with the verilog code. I will attach the verilog code...
  3. A

    [SOLVED] Bit select not declared -VHDL error

    Hello, I'm working with DFTadvisor. I am having a problem when I apply the command read_verilog b04_gate.v b04 is a benchmark design of Itc99. The error message is Did any one had this problem before. You will find below the VHDL file of this design because I think the problem is with...
  4. A

    [SOLVED] DFT - How to add derived clock in a design

    Hello ThisIsNotSam, Thank you for your answer. I would like to know if I have to add those clock by my self to the design, or if the synthesis tools could add them automatically. Thank you
  5. A

    How to apply external pattern source in mentor graphics tessent tool in DFT domain

    Hello, I'm having the same trouble. Did you found a solution? Regards,
  6. A

    [SOLVED] DFT - How to add derived clock in a design

    Hello guys, I am thankfull to be part of this forum. I'm working with a design including just one clock ( benchmark ITC 99 design). My objectif is to reproduce one of the straggered clock scheme (attached) that I found in this paper (Using Launch-on-Capture for Testing Scan Designs...
See more

Part and Inventory Search

Back
Top