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I have completed layout of my design. However, in one of the guard ring I am getting a ERC soft check error. Can someone please help me with understanding what exactly does it mean?
I am adding the pictures of the error i am getting and also the ring where the error is highlighted.
Sofcheck...
Dear all,[
I have a transient signal as shown in attachment. I run transient noise simulation too to check the effect of the noise
I dont get how to find the SNR in cadence.
I have searched alot and i dont understand how should i do it.
Is it ok to find the rms value of clean signal and rms...
I have to share my cadence schematic with a colleague working in different place.
Can we share the schematic as we share the gds of layout?
I mean can somebody help me how can u export the schematic and share with a friend.
Thanks
Hi all,
How does the overdrive voltage effects the maximum voltage swing??
a) If my VDD is 1.2V and overdrive voltage of M4A is 300mV, what can be the maximum output swing at output?
b) Incase the overdrive voltage of M4A is 100mV what can be the maximum output voltage then?
I have designed a mixed signal design and its drc and lvs are all clear. However, when I run the pex, it gives me error- LVS Completed - INCORRECT
Netlisting failed because terminal 'VSS!' specified in placed master 'Layout_ff/1_Channel_ff/symbol'
does not exist in switch master...
Hi all,
For the bonding Diagram, I want to download package library from europractrice website and use it.
However, after downloading the .gds of package library, when i import it to some library (package as shown in picture 2) all the layouts are empty.
I tried thatching different technology...
Hi ,
I am designing a circuit in 65nm cmos process which has different VSS connections for analog and digital part(VSS! and AVSS).
However whatever i do, i get the below 50, 50 errors as shown in picture attached.
Can someone understand from the attachment what exactly it means?
What is the...
I have designed a two stage differential Amplifier with CMFB as shown in second picture of schematic for using it as Bipolar shaper . For the sake of stability, first i check phase of OTA which is 90 around and i understand, it is quite good.
Now i have to check for common mode and differential...
I am to make output driver for my circuit. In lvds common mode voltage is selected to be 1.2v.
If my supply voltage is 1.2v, is it possible to implement LVDS? if not, what are preferable voltage requirements for LVDS and also for SLVS?
Dear all I am looking for doing triple well layout for an amplifier. I am using nmos_rf_6t . Though it seems easy for layout but but since there is a restrictions on Lenght and width so i had to use to use MULTIPLE Factor. For multiple factor 3, i get 3 segments for one nmos and each is kept in...
I have to to layout of 2 stage amplifer in cadence 65nm. For reference i am given a design in which i am feeling difficulty. In layout all mosfet bodytie_type is left to none.
I was wondering how can the bulk be connected to gnd or vdd if all bodytie_type is selected to be none?
Secondly, if we...
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