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Recent content by AlexVD

  1. A

    subthreshold n factor

    iexplorer, hi! If you have any PDK with monte carlo section , you can simulate it. without factory measurements its difficult to know. Best reguards
  2. A

    how to plot the current of the on-chip resistor after doing the post-sim?

    allennlowaton, From the calibre menu go to OUTPUTS and change output format to calibreview. "run HSpice from ADE" i mean to launch Analog Design Environment from Virtuoso schematic editor(Tools->Analog Enviromnment). Best Reguards
  3. A

    PLL---> VCO control voltage

    Ayyanar M , Try to check your cadence results whith a program for calculating the loop parameters (ADSimpll from Analog devices), or EasyPLL Loop Filter Design Tool from national semiconductor. AlexVD ---------- Post added at 13:04 ---------- Previous post was at 12:28 ---------- Ayyanar M ...
  4. A

    PLL---> VCO control voltage

    Ayyanar M , I have simulated your loop with next parameters: PFD freq=20MHz C1=130pF (standing alone), C2=3pF, R=12k, VCO gain is 1.78GHz/V, I=20uA, Fvco=500MHz The phase margin of your loop is about 1-2 degree!!! Recalculate your loop filter. Best reguards, Alex
  5. A

    PLL---> VCO control voltage

    Ayyanar M , hi! its look like your loop is unstable. PFD frequency is 20MHz? C-R-C filter is used? If yes, which value of R? Really VCO gain is 1.7GHz/V ?? Its so much. Best reguards Alex
  6. A

    how to plot the current of the on-chip resistor after doing the post-sim?

    allennlowaton, From calibre pex choose the output netlist format as calibreview instead of hspice. after that virtuoso schematic will be generated. Then run hspice from ADE and select interested current. if there is no possibility to change the format of the PEX netlist, you have to select (in...
  7. A

    how to plot the current of the on-chip resistor after doing the post-sim?

    allennlowaton, that tool you used for pex? Do you simulate netlist from command line or from cadence gui? Alex
  8. A

    Technlogy Porting in design from one technology to another

    Re: Technlogy Porting in design from ne technology to another terebin4, It's a translation of schematics and layuots from one PDK to another How this can be done.? - Read Virtuoso Layout Migrate User Guide from Cadence. Best Reguards
  9. A

    how to plot the current of the on-chip resistor after doing the post-sim?

    allennlowaton, Try to import netlist to schematic editor and simulate it.
  10. A

    How to calculate Slew Rate for Differential folded cascode opamp.....??

    hi ASHUTOSH RANE There is no any mistake in calculation, all right!
  11. A

    Better Alternative for MIM and MOM Capacitors?

    igorbog, If there is no documentation on PDK, The simple way to choose better capacitor- is to perform parasitic extraction by Calibre/Assura end check extracted netlist for parasitic capacitance. Best reguards
  12. A

    How to calculate Slew Rate for Differential folded cascode opamp.....??

    ASHUTOSH RANE, After tarnsient simulation you have to do direct plot differential output signal from Results->directPlot-Transient->transient difference Than you can deriviate this expression to calculate slew rate of differential output. Or use this expression in cadence command line...
  13. A

    PSSR of a Current Reference Circuit

    urn, You need to perform ac-simulation with specified ac value in suply voltage source. then you plot output curent. This Value is PSSR [A/Volts] AlexVD
  14. A

    How do I set a good static work point to a fully differential telescope OPAMP?

    yeknight, Show your schematic please, That Vth of mosfets and supply voltage of OPAMP? Best reguards
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    Two ways to test the linearity of a Switched Capacitor Integrator? Which is better?

    sharezao, Try to change analog options for simulation such as reltol and abstol. Also you can decrease time step. Best reguards
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