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Re: Signal ignoring initializers and initializing to random state
OK, I think we are confusing each other a little here. As I see it, there are two approaches we are discussing:
1. The method described in the application note to implement a mostly-internal POR circuit. This uses one external...
Re: Signal ignoring initializers and initializing to random state
OK, that's easy enough - but what drives the pin, in this approach? An external hold-off circuit?
Re: Signal ignoring initializers and initializing to random state
Can you elaborate slightly on what this "primary input" is? I've not encountered this term. What would drive this signal? I'm certainly keen to simplify this reset logic if I can!
Re: Signal ignoring initializers and initializing to random state
Thanks all. I didn't even realise that my startup counter might also be starting up in a state that prevented that init block execution, but I can see that's completely the case.
I've not got any external circuitry to do an...
Signal ignoring initializers and initializing to random state
Hi all!
I have a VHDL program that, despite all my effort to stop it, keeps initializing its signals in a random state. Sort of: it apparently initializes in the same state on each powerup, but the pattern that comes up I don't...
Not sure I follow you with the TCK crosstalk - while I see similar waveforms on all three lines, I presumed these were all due to the same line inductance properties and driver in the programmer. But they might be. The wiring is exactly as you describe - a bunch of wires with indiscriminate...
Hello all!
Apologies for the bad link. The correct one is: http://www.actel.com/documents/PA3_UG.pdf
I agree the signal looks bad. I will provide schematic/photo/layout when I get back to my computer. I think the board itself should be ok, and I expect my programming wiring is the most likely...
A little development. By adding a series resistance to the TDO line, and a series resistance and a 100pF capacitor (a LPF) to the TCK line, I am able to get the programming process to complete successfully. Reportedly successful. It erases, programs and verifies fine and without error. However...
Hi ads-ee, thanks for the response.
I have pull-downs (10k each) on the TCK and TRST lines, as that is what is suggested by the manufacturer (pg 359). There may be pull-ups on the programmer. I have no explicit termination on the TCK. I am going to add some capacitance more deliberately to...
Hi all,
I'm trying to program an FPGA - a Proasic3 - via JTAG from a LCPS programmer (functionally equivalent to a Flashpro3).
When all wired up to the header, I start the programming process. The reading of the device IDCODE and other status data works fine (at least, I get consistent and...
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