Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
tran simulation need more time to stablize.so maybe you can set the time of tran simulation to 1us.And there is another issue,the time step.you can set the max time step to be 4ps in the option box of tran .
hi,all the experts:
what is the advantage of this vco topology.there is a parallel combination of a nmos and a 1pF cap in series with the cross couple pair.what is the usage for this paralle combination of the nmos and large capacitor.thanks
BR
1646791101
Is it to reduce the phase noise?
when calculating the SNR of adc，should the bandwidth of noise be 1/2fsample？
when calculating the SNR of adc，if i want to calculate all the noise，should the bandwidth of noise be 1/2fsample？in the book，its said that the quantization noise of adc is distributed in the range from zero to...
how to decide the specs of in-band phase noise of a bluetooth pll? I think the outband phase noise of a pll ,for example ,phase nosie@1MHz or @2MHz,are decided by the adjacent channel interferience,because of the reverse mixing of LO.But ,how to decide the spec of the inband phase noise of a...
Re: Is it right to understand the Zopt（optimized noise impedance）of ind degenarated l
thanks a lot ,Sir.
I got some equations of Zopt from the paper
**broken link removed**
The value of real part of the Zopt is the first equation. A and B1 are demenstrated by the last 2 equations. Cgs is...
Is it right to understand the Zopt（optimized noise impedance）of ind degenarated lna
Is it right to understand the Zopt（optimized noise impedance）of ind degenarated lna
Today i took part in an interview.The interviewer asked me to saysomething about lna.At first,I wrote the power matching...
How much salary can a rf/analog ic design engineer get in usa and europe
hello,How much salary can a rf/analog ic design engineer get in usa and europe?
the expeirience:The enginner has a MA and 8 years working experience: 5 years experience in mixed signal module :phase locked loop...
hello.Is there anyone who could tell me the procedure of design a inductive source degenerated LNA at 2.4GHz?
I am designing a source degenerated LNA. And I used a cascode NMOS .And some collegue told me that at first I should sweep the width of gm nmos while setting its length to...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
