Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Re: to_unsigned with two arguments vhdl
hi,
I SYNTHESIZED the filter and introduce fixed point, but when I convert it to verilog code still it produce signed input/output which is not synthesizebale with desigin_vision.
Do you have any idea?
I have tried to give only unsigned input/output...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.