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hi Dayn.....
During synthesis assign a timing constraint for specified inferred clock......u can rectify from this.
it is only defining the clock type(inferred,derived,declared and system).
hi....i am new to verilog,i wanted to know what is inferred clk??????...
i am getting warning like
( " Found inferred clock toplevel|clk with period 40.00ns. A user-defined clock should be declared on object "p:clk" )
can any one of you explain me about this.........
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