Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Throughout my layout career I have seen layout engineers going mostly to analog design (75% approx.), some to digital layout and synthesis (10%), some to concept engineering (5%) and some leave the field for good (10%) ;-). So I have not seen shifts from layout to testing or any kind of lab...
Re: what is the diff. between decoupled and coupled in Assur
Hi pit1000. Do you have the whole document from which you showed these 2 pages? I am trying to find a assura workshop but it seems there is none. Thanks
Hi all! Thanks for the replies, really helped me with some ideas.
I still have 2 questions:
- the guard ring surrounding the cell must be as close as possible to the cell, or at some distance?
- do you know some documents with real experiments of guard rings? I mean results of test chips...
triple guard ring layout
Hi!
No, i'm not asking about tap guard rings. I'm asking about a guard ring surrounding a digital cell that is really noisy and must be isolated. I read that the disturber must be surrounded by n+ guard ring connected to it's own supply, and that the disturbed cell...
guard ring for silicon die
Hi!
I have a question about layouting the guard rings in CMOS technology. n+ or p+ guard rings are connected to power or ground.
Hastings of other books speaks only in general about these rings. But i have some small issues that i cannot find in books:
- how can i...
Re: IR voltage drop
OK, thank you very much for your answers. So, what i discovered so far, there are 3 software tools: Cadence - Voltage Storm, Synopsys - AstroRail, and Magma - BlastRail.
Well, in digital, it's clear, it's Magma, but i also understood that AstroRail is for digital.
I need...
Hi Firas,
Indeed, fixrouter4400 is right. In Virtuoso Layout you do the layout just looking at the schematic, but it (the schematic) does not influence the layout tools itself.
In layout XL, you can import the netlist from the schematic into the layout (generate from source). That is the first...
Re: Why?
Because in both bipolar and cmos technology, the npn and the Nmos transistors are the most important parts in the technology, and it is easier and NORMAL to use a p-substrate. (study the device formation of nmos and npn)
Re: LVS global error:layout has changed in library since ext
Try saving and closing all the layout windows, and the extract again. If it does not work, you should contact some IT guys, because something is wrong.
ic chip layout beginners
My friend, i was asking for layout books before, like you. But believe me, you can get or buy 100 books, if you do not work with the layout tools, and if you don't ask collegues about layout issues, you won't learn anything. You must do the layout, you must break your...
Re: LVS
The "not cross-match" error in LVS indicates that the device/net connections in layout are not the same as in schematic. It may be that you missed one connection, or more. So, this are : DEVBAD.OUT and NETBAD.OUT. The last error, TERMINALBAD.OUT means that that particular terminal IS in...
Hello,
I am interested in software for IR voltage drop analysis in integrated circuits. Besides Voltage Storm from Cadence, do you know any other tools for this task?
Does anyone know any documentation for IR voltage drop analysis?
Thank, Alecs.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
