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There are four kinds of PLL jitter:
1.period jitter
2.short term jitter
3.long term jitter
4.cycle-to-cycle jitter
What is the significance of the different kinds of PLL jitters?
Now I think the "period jitter" can be considered as one part of "clock uncertainty" for STA normal "setup check"...
Here is the definitions of "PLL period jitter" and "PLL cycle-to-cycle jitter" bellow.
Which jitter should be considered as "clock uncertainty" in STA (just for setup check, no affect to hold check)?
Period Jitter (A), (JEDEC Definition - JESD65)
The edge deviation to the ideal FOUT when...
It'said that the design using useful skew for timing optimization is susceptive of the operating condition variation-temperature,voltage,process...
And why?
zero skew clock tree also have clock buffers which have PVT variance.
Re: Frontend vs. Backend
I'm a BE engineer, in what way the knowlege of FE help my job?
If I'm a FE, what the knowlege of BE should I know? Waht's the useful things it offer me?
Maybe I should make a division between Architecter/RTL coder/verificer from FE job. Everyone would say the knowlege...
I often read that 10% IR drop may cause 7% performance degrade..
Does the 10% mentioned here represents VDD drop+VSS drop? If so, what is the deffernt between 2%VDD/8%VSS and 5%VDD/5%VSS?
I'm not sure about the impact of VSS drop to output high voltage(CMOS, voltage pull up by VDD, seems...
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