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here s my code...
IBUFGDS #(
.DIFF_TERM("FALSE"), // Differential Termination
.IOSTANDARD("DEFAULT") // Specifies the I/O standard for this buffer
) IBUFGDS_inst (
.O(CLKIN1), // Clock buffer output
.I(clk_p), // Diff_p clock buffer input
.IB(clk_n) //...
Hi i'm using Xilinx ISE 13.2 version. i'm generating the mig core and generating the clock through MMCM. the MMCM clock is further being connecte to the MIG. but i'm facing problems in translate stage. i'm getting these errors. My Synthesis is fine. kindly help.
:sad:
ERROR:NgdBuild:455 -...
[I]
Thanx 4 d response... but thats my actual question "why is it limited to [3:0] why not more than that?" it all depends on the designer, he can even design it to be greater than [3:0]...
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