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Recent content by ajay181

  1. ajay181

    How to do the layout efficiently for multiple current mirrors

    Hi, I am not able to clearly understand the query here. Are you mentioning that you have one diode connected device which mirrors the current to more than one device ? Cheers Aj
  2. ajay181

    Interdigitisation is preferred over Common Centroid for Current mirror Layout. Why?

    Hi Friends, I have read in most articles/books that for current mirrors Interdigitisation is better. My query is : Are there any drawbacks of using Common centroid for Current mirrors ? [assuming the routing complexity is taken care of] Same way what is the drawback if I go with Interdigitised...
  3. ajay181

    skill function leCreateContact..

    Hi all, the skill function leCreateContact is available only in ic5, is there a substitute for the function in ic6 ? I am using ic6.1.4. Thanks in advance... Ajay
  4. ajay181

    why ggNMOS used for ESD doesn't break down under stress ?

    thanks all..
  5. ajay181

    why ggNMOS used for ESD doesn't break down under stress ?

    Hi all, Can anyone explain why ggNMOS used for ESD doesn't break down under stress , eventhough gate is shorted to gnd ?
  6. ajay181

    About CMIM mismatch????????

    Hope you have used unit caps of same size with common centroid arrangement ? the ratio match between cap can be calculated by checking the extracted cap values between them.
  7. ajay181

    Cadence Skill- closing forms

    Hi all, Opening and editing form, works fine but the form cannot be closed through skill code. Can anyone suggest an alternative ? >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> if(leDisplayOptionsForm->type->value == "lines" then leDisplayOptionsForm->type->value = "dots" else...
  8. ajay181

    Layout of DC-DC Switched converters

    Hi all, can somebody give details regarding the CMOS layout of DC DC switched converters, and where can i find details regarding the same..
  9. ajay181

    Common centroid arrangement in Capacitor Layout

    common centroid capacitor arrays ok, now i am using Tr Cap ie. Gate 'plus' and S/D shorted for 'minus' . So it's better to use S/D for the common share node right ??
  10. ajay181

    Common centroid arrangement in Capacitor Layout

    centroid arrangement matching hi i am back :) erikl you said that it's advisable to use the common share node be made the bottom node. can you explain the reason ?
  11. ajay181

    Common centroid arrangement in Capacitor Layout

    common-centroid capacitor layout Thanks guys, for the valuable points
  12. ajay181

    Common centroid arrangement in Capacitor Layout

    common centroid is better for matching capacitors Thanks erikl, yes, dummy cap cells will be put as a ring surrounding the active array. But the confusing part is that we have lot many possible arrangemnts,.. like one below is another possibility.. A A B A B C D A A E C B A B A A so how to...
  13. ajay181

    Common centroid arrangement in Capacitor Layout

    common centroid is share common top Hi all, a situation were i need to employ common centroid pattern for capacitor layout. Can the following be called a common centroid pattern..?? A A A A B C D B B E C B A A A A
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