Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
indeed,just like andy1 saying.There are usually a reference clock in many CDR design.reference clock could improve aquisition time and design circuit much easier.In my thesis,I design a CDR with referenceless clock. i met many issues that would not exist in CDR with reference clock.So...maybe u...
i guess your architecture are Dual-Loop without reference clock signal...you need PD FD CPs LPF&VCO..Linear phase PD is suitable for your design. It's okay for 10MHz data rate,all of the design skills you can check the papers.The close loop analysis of PD part is similar to the PLL,one of the FD...
Ring Oscillator
The bandwidth of the bias generator is typically set equally to the operating frequency of the buffer stages so that the bias generator can track all supply and substrate voltage disturbances.(quoted from the paper)
vco psrr
i think u should to know the meanings of symmetric loads,u could search the paper "Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques" by John G. Maneatis...Besides, u should design another circuit(self-biased replica stage) to provide Vctrl and Vbias which the...
All of the products are depend on the MARKET!! No market,no money!! In brief,10m/100mb is enough for most people,so the "Gigabits" network is dispensable.
By the way,if you want to replace "cable" with "optical",there are so many stuffs necessary to be changed...But my reserch topic is about...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
