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Recent content by ahmedkhalaf

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    PIC18F4550 with Parallax USB datalogger via UART

    I'm working on a Flash memory based datalogger using Microchip PIC18F4550 and **broken link removed** which is based on **broken link removed** I'm developing my prototype on MikroC so everything can be a piece of cake :( My problem is interfacing the uC with the datalogger, and...
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    Implementing MIPS compatible processors

    Hi There have been some projects on opencores that are microprocessors implementing (or partially implementing) MIPS instruction set. Is it legal to implement MIPS instruction set ? and what considerations one should take ? Note: I'm doing some research on performance and I'd like to apply...
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    90 to 45nm Technology benefits and simulation ?

    Hi, How does the shift to a smaller technology affects gate delays ? how can a specific technology simulated on Orcad Pspice I'd like to ask about simulating SOI CMOS in Orcad PSpice? Thanks alot
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    CMOS gates - Orcad PSpice 9 Simulation

    cmos orcad library Hi I was wandering if there any tips regarding CMOS logic circuit simulation in Orcad PSpice the main goal is Gate level (and if necessary Transistor level) simulation and precise/realistic Timing simulation shall I build gates from ordinary transistors ? IRF9530 for...
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    Gate Delay dependent circuits

    xilinx isim transport delay Thanks FvM and omara007 I'll do some more research and get back with more questions :)
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    Help with: Gate Delay dependent circuits

    Please take a look on this thread, if you can help with it post a reply there to centralize Smile thanks
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    Gate Delay dependent circuits

    gate delays in verilog Thank you FvM... :) I dont know if ISE Simulator can do it :( I checked the synth. output ... I can get the output I want with some configuration, but I still dont know how to simulate that accurate timing. Thanks again Added after 7 minutes: I have posted the...
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    Help with: Gate Delay dependent circuits

    Please take a look on this thread, if you can help with it post a reply there to centralize :) thanks
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    Gate Delay dependent circuits

    fpga gate delay Hi, I'm trying to implement a ring oscillator using series of inverters, and I need to study the smallest changes in time, but no use with the ISE simulator: I get the signals changed in the same instant of time. (I'm using Free ISE 10.1 WebPack) also I tried a series of...
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