Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by ahmedalzaabi

  1. A

    Sequential design in VHDL

    CE0 and CE1 should be the j/k ff (T FF)input equations, your declaration is correct, you need to assign values for them.. look at project one for the equations.. RCO is your 3 to 8 decoder selected output... as far as i remember its something like q0 and q1 and input or the q0' q1' and input'...

Part and Inventory Search

Back
Top