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Recent content by aftermorning

  1. aftermorning

    Simulink And System VUE

    it sems that systemview is a former version of simulink.
  2. aftermorning

    Problem wirh DDR SDRAM controller targeting on board XUPV2P, Virtex-II Pro

    DDR question you can try your ddr controller at a lower freq to see whether it can work well.
  3. aftermorning

    Verilog Code PLEASE HELP!!!!!!!!!!!!!

    Umair_ali gets the point and i think you can upconvert the main clock with the DCM. then the accuracy performance will be better.
  4. aftermorning

    iwant complete vlsi fpga mini project withcodeusing verilog

    opencores is cooool!
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