Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by ads2017

  1. A

    Compile-time forces (NCSIM and VCS)

    Code generation scripts prevent this :( And besides, there's no natural location for the forces to reside - I'm forcing configuration registers, not signals coming out of the missing modules. The test input can't be modified. Except that 1) that would prevent the use of emulators, and I...
  2. A

    Compile-time forces (NCSIM and VCS)

    I'm using a force to compensate for the fact that I've removed parts of the DUT to speed up testing, and I now need to automate this process. Since not instantiating parts of the DUT is inherently a compile-time decision, the compensation should be too. So ideally I would like to force signals...
  3. A

    Compile-time forces (NCSIM and VCS)

    I know but would that not require a whole new SV file just for the forces? I would prefer to specify them on the command line if possible.
  4. A

    Compile-time forces (NCSIM and VCS)

    Hi I understand that it is possible to force a signal at compile time (with NCSIM at least) so that it will have a constant value every simulation without the need for run-time intervention. However, I can't seem to find any documentation for this on Google. Note I would rather not modify the...
See more

Part and Inventory Search

Back
Top