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yes, that was my asumption, but it depends on your final circuit. According to your picture, M1 is a common source NMOS transistor, M4 is a PMOS current source, M2 is a PMOS level shifter, M3 is a PMOS tunable current source and I'm assuming M5 will be an NMOS and that's why you will need a...
I'm trying to simulate a Class D amplifier with hysteretic self-oscillating modulator but the PSS simulation is not acepting the configuration.
Basically the self-oscillating system frequency (fs around 500 KHz) will be modulated by an audio signal (fin around 1 KHz) and fs will be varying...
I will assume that you have a power supply high enough to have 5 transistors stacked (one current source, two for cascoded input and two for cascoded load). If you want to reduce your UGB you need to add more output impedance or increase the transconductance of your input stage. You can achieve...
For 12 bits resolution you will need around 75dB of SNR, assuming that your signal bandwidth is around 100Hz, you can easily achieve that SNR with an OSR of 50 with a single bit quantizer and a second order loop. The main issue is your input signal level, since it is a sensor I will assume that...
The filter type will be determined by your requirements of SNR. Are you implementing a continuous time or discrete time sigma delta? What is your target signal bandwidth,target SNR, desired filter order, OSR. Everything matters when trying to decide which filter is best for your application...
This looks like a linear low dropout regulator (LDO). I'm assuming that all transistors are PMOS except the Vx input transistor that is NMOS and all in saturation. Vtune is a current source that will change the amount of voltage shift that Vout will have. The NMOS with input x is operating as a...
I'm not sure what is your doubt. But the difference for choosing a HC part or a HCT part depends in what input logic levels do you have. As an example if my logic leves are 3.3V for logic '1' and 0V for logic '0', then I would use the HC part. But if my logic is 5V for logic '1' then it would be...
Taking into account the Cgd of M1 and M2, you have a total of 3 zeros. Two high frequency zeros, z1=gm1/cgd1 and z2=gm2/cgd2. The other zero comes from the gain boosting amplifier. The pole at its output gn2*cn2 will be a zero in the main transfer function. gn2 is the conductance at node N2 and...
Low efficiency can be caused by several things. Which switching frequency did you use?, this is very critical since the losses from the drivers are proportional to this frequency. The datasheet states that it can go from 650KHz up to 1.3MHz. Check if your chosen frequency is within this range...
The description document that you provide explains pretty much everything with detail. If you want an overview of what is happening, I can tell you.
Is a flyback inverter controlled by PWM, it has dead time control and non-overlapping provided by IC5/6/8. The IC1 is implementing an square wave...
You can easily find the definitions for those parameters if you look at the datasheet for the part.
VIH: High level for input voltage or input logic '1'
VOH: High level for output voltage or output logic '1'
VIL: Low level for input voltage or input logic '0'
VOL: Low level for output voltage...
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