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Hello All,
I found the solution, I had to add the line: .option PROBE to my source file. This works together with the
.probe statement in the Analysis section. This question can be closed.
Best regards,
. option PROBE
** Testbench setup
.include "tb_bandgap.hsp"
.hdl...
Dear All,
I want to limit the output of my simulation. Now all nodes and many subcircuit level nodes are
saved in <ckt>.out.tr0 I like to have only a few hierarchical levels in the output. Probing a few nodes doesn't give the required result. Does anyone have an example?
I use this now:
**...
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