Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Many, many thanks for the reply.
So my code;
//---------------
reg [6:0] address;
reg clock;
wire [15:0] q;
Spriterom u1(
address,
clock,
q);
initial clock=0;[/B]
//--------------
Is this correct or should I be using "clk" instead of "clock".
During the
H_SCAN > HZSYNC+HBACK_PORCH
and...
Hi,
I have created a MIF file containing 100 x 16bit values. The values point to a colour palette which contains the RGB values for 10 colours.
In Quartus Prime Lite I have used the IP Catalogue to create a ROM: 1-Port file
My top Verilog HDL file references the ROM file which when compiled /...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
