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These files belong to BOOKSIM simulator ( https://github.com/booksim/booksim2). an islip kind of allocator which used inside of the router.
router files inside of ../src/routers/router.cpp
and
Islip file inside ../src/allocators/islip.cpp
In router any time we need to allocate switches/ports...
Hello,
In Attached file there are four files (router.cpp, router.hpp, islip.cpp and islip.hpp) for same project.
In router.cpp, there is a parameter which is (id or _id), that indicate the id of a router, for example, router 0 or router 1.
Now, I need the value of this parameter in...
Thank you for your advice. I will read the document, but we can use this IP to designing a switch, it would be nice if I have something related to designing a switch from scratch.
Bests,
Hi,
I am going to design An Ethernet switch on FPAG. Our input data could have priority also we need to design the switch on real-time applications. So, in this case, there is another protocol called TSN. But since the design of the TSN switch at the beginning maybe needs too much time, I am...
thank you for answering.
about X', i already have this problem in address as i find out i connect 1 and 0 in some connetion. but about delay the write to the ram until FP IP would have the valid, i tried it but i couldnt solve the problem.
i wll appreciate to give me some clue to find out.
Hi,
I want to design a system with VIVDAO 18.3 version(Virtex-7 and xc7vx485tffg1157-1) by using VHDL code and also used FP-IP (latency = 2) and RAM IP.
I saved numers in coe file: address 0 to end have these value= > c190 0000, 4118 0000,411c 0000,4000 0000, c000 0000, 4000 0000 , c000 0000 ...
just for determine number of level changer, So I can use it, whenevre 2 times input level changed, output = input after that output = 0.
So with this idea output show just first pulse of input.
So, if this cant work. what is your advice for me, I want to design a simple gate level circuit that work like this simulation :
It means in output I need just first pulse of my signal.
I write this idea for my purpose with verilog code
module pulseD(
input data_in, rst,
output reg data_out);
reg [3:0] count;
reg temp_in;
always @(*)
begin
temp_in <= data_in;
if (rst) begin
count <= 0;
end
else if (temp_in != data_in) begin
count <= count + 1;
end
end...
Hi, I want to design a circuit that :
input is pulse with different width, but i just want to have first pulse in output. do you have any idea to design this with gate level.
I will appreciate if someone help.
thanks
I changed the code several times. my first idea was, just multiplier is sequential , and other part combitional. but after that I change it several times to get answer
Re: Need help for write verilog code for recurrent block
yes, it should be combitional
- - - Updated - - -
this code it just for one block ?
I understant that two output of this block is always 'x'
`timescale 1ns / 1ps...
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