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Recent content by ADITYAVARDHAN

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    Information about VHDL e-book

    FPGA PROTOTYPING BY VHDL EXAMPLES,Pong P. Chu
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    verilog interview question

    Given the following Verilog code, what value of "a" is displayed? always @(clk) begin a = 0; a <= 1; $display(a); end Please answer the question with reason. Thank you
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    How to insert delay in digital signal?

    you can also use D-flip flops to get delay
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    post synthesizes simulation ,mapping ,place and Route .

    The steps for post synthesizes simulation, mapping, Design constraints, static Timing analysis and place and Route vary depending on the type of device used(Altera/Xilinx). The below link contains the information for Altera devices...
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    FPGA and VHDL/Verilog for Begineers

    you can find some examples at **broken link removed**
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    FPGA and VHDL/Verilog for Begineers

    FPGA prototyping by Verilog examples: Xilinx Spartan -3 version‎ by pong p.chu FPGA prototyping by VHDL examples: Xilinx Spartan-3 version by pong p.chu These books have a lot of examples and they are explained step by step.
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    4-bit parity generator

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    Problem in pin assignments

    I am using verilog
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    Problem in pin assignments

    HI, I am using Altera DE1 board.Is it possible to assign 2pins to single output in the pin planner.I need an output to both the LED on the board and the same output to the GPIO(general I/O pins).If so how can I do it? Thanks for your help.
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    Advanced Digital Design Books with verilog HDL

    You can find good examples in 1) Verilog for digital design by Frank Vahid. 2)FPGA prototyping by Verilog examples by Pong P. Chu.
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    6:2 Mux implementation

    I think it is not possible because we need select lines to select the output for a MUX.As we need 2 outputs we must have two select lines at the same time which is not possible.
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    Verilog array of registers synthesis problem

    S1 : temp1 = data_str0[0] + data_str0[1]; S2 : temp2 = temp1 + data_str0[2]; S3 : sum = temp2 + data_str0[3]; I think the problem may be because you are using the blocking statements.Blocking statements create latches.So make the temp1,temp2,sum non blocking statements. S1 : temp1 <=...
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    frequency counter & 555 questions

    A frequency counter measures and displays a signal. ---------- Post added at 03:03 ---------- Previous post was at 02:36 ---------- A 555 operating as a monostable multivibrator has a C1 = 0.01 F. Determine R1 for a pulse width of 2 ms. Answer:182 Formula pulsewidth=1.1*R*C I think it is...
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    Problem in sound from Altera DE1

    I am using Altera DE1 board.I am able to produce the sound from the de1 board but i am unable to set the volume.Is it possible to set the volume?
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    How to find number of registers in a design?

    If you compile the design in the compilation report we get the number of registers and the gates used in FPGA's.If I am wrong please correct me.
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