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Recent content by aditik19

  1. A

    multiple packed dimensions are not allowed in this mode of verilog

    yes i have added it and it showing error module sobel_operator ( input clk, input reset, input [7:0] in_pixel, output reg [7:0] out_pixel, input [7:0] v_blank ); (* IOSTANDARD = "LVCMOS33" *) // Add this attribute to specify the I/O standard reg signed [7:0] h_kernel [0:2]; reg...
  2. A

    multiple packed dimensions are not allowed in this mode of verilog

    hi, I think the design may not need any compile-time switches to function correctly that's why but you can suggest me and please let me know which i need to improve and add the part in my design Thank you Best Regards
  3. A

    multiple packed dimensions are not allowed in this mode of verilog

    module hdmi_sobel ( input clk, input rst_n, input [7:0] in_pixel, output reg [7:0] out_pixel, output reg [7:0] h_sync, output reg [7:0] v_sync, output reg [7:0] de, output reg [7:0] h_blank, output reg [7:0] v_blank ); // Declare the HDMI synchronization signals reg...
  4. A

    multiple packed dimensions are not allowed in this mode of verilog

    i am using vivado
  5. A

    multiple packed dimensions are not allowed in this mode of verilog

    localparam integer x_kernel[2:0][2:0] = '{ '{-1, 0, 1}, '{-2, 0, 2}, '{-1, 0, 1}}; Error - Syntax error near "'". Warnings - extra semicolon is not allowed here in this dialect. use SV mode
  6. A

    multiple packed dimensions are not allowed in this mode of verilog

    Still there is an error localparam integer x_kernel [2:0][2:0] ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}}; wrong element type in unpacked array concatenation multiple packed dimensions are not allowed in this mode of verilog
  7. A

    multiple packed dimensions are not allowed in this mode of verilog

    localparam x_kernel [2:0][2:0] ={ {-1, 0, 1}, {-2, 0, 2}, {-1, 0, 1}}; error parameter 'x_kernel' with unpacked dimension should have a data type and parameter with unpacked dimensions is only allowed in system verilog 1682511165 module edge_detection ( input clk, input rst...
  8. A

    multiple packed dimensions are not allowed in this mode of verilog

    how to declared can you please guide me? thank you
  9. A

    multiple packed dimensions are not allowed in this mode of verilog

    tried this but still getting error like multiple packed dimensions are not allowed in this mode of verilog and concatenation unsized literal: will interpret as 32 bits
  10. A

    multiple packed dimensions are not allowed in this mode of verilog

    // Define Sobel operator kernels localparam [2:0][2:0] x_kernel ={ "-1, 0, 1", "-2, 0, 2", "-1, 0, 1" }; localparam [2:0][2:0] y_kernel = { " -1, -2, -1 ", " 0, 0, 0 ", " 1, 2, 1 "}; i am getting error i want to implement it on vivado zcu106 board for edge detection for image processing and...
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