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Re: LUT in VHDL is getting to many ressources
The LUT are made by me in VHDL as follows:
if (RESET_N = '0') then
lut_output <= (others => '0');
elsif rising_edge(mclk) then
lut_output <= lut_data(to_integer(unsigned(lut_input)));
end if...
LUT in VHDL is getting to many ressources
Hi,
I'm making a project where I need to use 4 different LUT. My FPGA is a Microsemi and I'm coding in Libero.
They have two by two the same input for the LUT (LUT1 and LUT2 has the same input and LUT3 and LUT4 have a different same input). LUT1 and...
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