Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by adelezy

  1. A

    What is the flow fo vco calibration?

    help: vco calibration? help: what's the flow of vco calibration ?
  2. A

    Is there good lecture about offset phase locked loop?

    Thank you very much. :D
  3. A

    Is there good lecture about offset phase locked loop?

    urn_ubn_se_liu_diva-1838-1__fulltext.pdf Is there good lecture about offset phase locked loop?
  4. A

    LC VCO with switch cap architecture

    vco switch cap I have met the similar case. My idea is that the mos doesn't turn off throughly. The spectre will get a wrong convergence.You can have a try. And I did so, and i get a resonable result after that.
  5. A

    what's the spec of synthesizer for GSM and for WCDMA?

    Different communication standards have their specical working frequency range. As for frequency synthesizer, how to define the spec ?
  6. A

    How to estimate the fmin and fmax of a frequency divider

    Dear all: The CML frequency divider has a operating frequency range fmin~fmax, right? But how can I easily estimate the range? And why it has a fmin? How should I understand the fmin? Thank you, adele :D
See more

Part and Inventory Search

Back
Top