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Recent content by adap

  1. A

    Looking for One Hot encoding tutorials

    Hot Encoding If you mean for one hot decoding in state machines have a look at the following link: **broken link removed**
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    Function for a square root of a generic-length std_logic_vector in VHDL

    sqrt vhdl You can have a look at the following paper: https://cis.k.hosei.ac.jp/~yamin/papers/ACAC2000.pdf It describes a square root algorithm and its implementation
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    What's the advantage of writing VHDL that can be recognized

    You should use the (when others =>) in the case statement. This also creates latches.
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    ASIC min. reguired knowledge

    I have not read the ASIC Handbook but I know about the Aplication Specific Integrated Circuits book. This book is a bible for ASIC design. It has every step from coding to floorplanning. It's an engineering book and you can use it as a reference. Maybe as a beginner it will be difficult to read...
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    What does FDMA stand for?

    fdma?? You can have a look at the following link: https://en.wikipedia.org/wiki/FDMA
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    Help for halfband filter design documents!

    There is a paper in the forum that concerns halfband filters: and also a book that has a paragraph for this filter:
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    error in model sim II 5.6e

    You have forgotten to declare what type (reg or wire) A, B, C, D, Y are and if they are buses or not.
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    Who can help me ? thank for you help!!!

    I believe the two codes in this link will help you: **broken link removed**
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    Help me jump over counter values in a code

    Help need You need to reset the counter when its value is 4 to jump over the values which are greater than 4. So: ...... begin if (count == 3'd4) count <= 3'd0; else count <= count +1 ; case (count) ..............
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    Problem with real numbers

    You can work in the RTL code with std_logic_vectors. In the testbench you can convert the real numbers in std_logic and vice versa to give data and take expected results. In the following link, there is a part of code that does these conversions: **broken link removed**
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    Can anyone help me understand this code for halfband filter?

    r0 is produced directly from d0 which is 12 bits while the other (r1..r5) are produced by adding signals, so they are extended by one bit to avoid overflow. The calculation of the results are: result1 = r5 - 16*r3 result2 = result1 + 2*r1 result3 = result2 + 4*result2 result4 = r1 + 64*rr1...
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    Verilog codes for clock divider

    Re: CLK Divider HELP There is no need to use dual edge flip-flop. That part of the verilog code is as writing in VHDL the following: process(clk_50mhz, rst_n) begin if reset = '0' then ........ elsif rising_edge(clk_50mhz) then .......
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    When should I do signal transition?

    Signal transitions If you interface with external components always register the inputs you take and the outputs you produce, so they are stable.
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    how to compare two data in 2s complement form?

    In order to check two numbers you have to subtract them. If the MSB of the result is 0 and the number of the result (the remaining digits without the msb) is 0 then the two numbers are equal. If the msb of the result is 0 and the number is /=0 then the result is positive which means that if...
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    How about signed adder?

    overflow adder If you want to add two 6 bits signed digit, then the results will be 7 bits. You sign extend the MSBs of the two numbers to have a result of 7 bits. For example if you add the 6'b10_0110 (which is -26 in 2's complement) and 6'b00_0110 (which is 6), sign extended (7'b1100110 +...
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