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Recent content by adamsogood

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    Verilog Question about Always sensitivity list

    Hi, can anybody explain the "*" in the sensitivity list in the following verilog code. What's that for? thank you. always @(*) begin if (!reset) begin A_r <= 1'bz; B_r <= 1'bz; line_en <= 1'b0; end else begin if (line_en) begin A_r <= #Delay_rd B...
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    Modelsim warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    modelsim compile error 1035 very informative and helpful...thanks.
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    Modelsim warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0

    modelsim runtime options this is an issue related to numeric operations in your simulations. for example, your logic wasn't properly initialized such that some illegal/undefined numeric operations happened, like divided by 0; multiply 'z', 'x', 'u' etc. use a text editor to open your modelsim...
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    XUPV2P and DDR memory modules

    xupv2p supported 256mb I think it is ok to use pc3200 DDR if pc3200 DDR2 is working on your board. According to my experience, DDR2 can work in harsher scenarios than DDR. The former needs less power, supporting higher frequency. All these thing make DDR2 more difficult to meet the timing...
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    XUPV2P and DDR memory modules

    what is 256mb ddr! memory modules means Hi, I think you are confused by the following two items 1.RAM PQI 256MB DDR PC3200 - 200/266/333/400 MHz 2.RAM Super Talent D27PB12C 512Mb DDR PC2700 - 266/333 MHz In fact, PC3200 means that it is running at 200MHZ ONLY. nothing to do with...
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    Problem with uninitialized signals when running VHDL simulation on ModelSim

    modelsim uninitialized value Hi, folks, Thank you for all your replies. Actually, the problem results from 'X'/'U' signal assignments, but the 'X'/'U' are not caused by improper initialization. it is all about the bi-directional signals. I am designing a DDR2 memory controller. In the very...
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    Problem with uninitialized signals when running VHDL simulation on ModelSim

    Hi, I have issues when I am running VHDL simulation on ModelSim. The problem is that some signals are not initialized properly (because it is a big design, so i can't assign the initial values to each signals). The uninitialized signals may assign 'X' and 'U' values and cause some unexpected...
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    why Xilinx doesn't support Dual-Rank DIMM

    dual rank fpga I don't think that's the case. because DUAL-rank SODIMM is useful for networking-based applications. Lots of customers desire this function. :)
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    why Xilinx doesn't support Dual-Rank DIMM

    mig dual rank Hi, I am wondering why Xilinx MIG2.0 doesn't support dual-rank DIMM? based on my testing, the IDELAY taps for both ranks are very close. thank you. adam
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    Xilinx MIG2.0 DDR2 memory controller

    +ucf +dqs +offset Hi, My problem finally got solved. Right now, my DDR2 memory controller is working at 300MHz and passed some rigorous memory tests. there are two ranks in my DDR2 SODIMM and one of them is unused. The issue turns out to be that I forgot to drive the rank select signal high...
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    Xilinx MIG2.0 DDR2 memory controller

    ddr2 calibration xilinx the delay on DQ/DQS should be configured dynamically on-the-flight to offset the variations on voltage, process, and temperature. I did modify the ucf file generated by mig2.0 to fit into my hardware board. i believe that the modifications are correct and working well...
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    Computer architecture forum.

    how about this one https://www.cs.wisc.edu/arch/www/ and this one https://groups.google.com/group/comp.arch/topics both of them are interesting.
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    Xilinx MIG2.0 DDR2 memory controller

    xilinx ddr2 calibration Hi, I am using Xilinx Virtex5 to build a DDR2 SODIMM memory controller. It is working well at 200MHz while having calibration problems at 300MHz. after carefully debugging and simulation, I think that Xilinx calibration algorithm didn't work well for big skews (about...
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    PLL and DCM in Virtex5

    dcm pll Hi, anyone can tell me the difference between PLL and DCM in Virtex5 in terms of pros and cons? thanks.
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    PLease Vote: Electronics Engineer Vs Computer Engineer

    it is a hard decision. too close to call. I go for a dinner and there are two main courses: steak or lamb shank. which way you go? ahhhhh.....
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