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Recent content by action taker

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    FPGA Design, Digital Clock

    great. thanks for your time and help. regards
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    FPGA Design, Digital Clock

    that looks interesting. i've wrote this code shown in the image basiclly what i've done is, i took all the signals from the BCDs s inputs and i used if statements to decide which signals to display and assigned them to the output, the output would be hh:mm, then if the counter is 100 i...
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    FPGA Design, Digital Clock

    ok, i have thought about this even before i post, but since i have three BCDs and each one has two output signals, that means i'll have six inputs to the multiplexer, right? can i create a multiplexer with four outputs?! and each output will be connected to a 7 segment, if this can be done then...
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    FPGA Design, Digital Clock

    i am trying to display it periodically, that is why i have added a delay counter that counts for 4 seconds before displaying the seconds but my problem is i dont know how to connect the ss output to the 7 segments. the other 7 segments are connected to the hh:mm . how can i connect the ss to...
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    FPGA Design, Digital Clock

    thanks for your replay ads-ee, i built three counters hours,minutes and seconds and for each counter i've connected a BCD. each BCD has two output signal like the following hh:mm:ss. so do i or the two BCD signals then connect it to the MUX?! - - - Updated - - - it has three push buttons and...
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    FPGA Design, Digital Clock

    Hello, I've built a digital clock using QuartusII. it shows hours, minutes and seconds. teh testbench works fine. i want to implement the design on an FPGA, Cyclon III. the problem is, the FPGA has four 7 segments, how can i show the seconds?!. i tried to add a delay counter to show the seconds...
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