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I agree with calculus, for transistors in series, you will add up the lengths with width remaining the same and for transistors in parallel you will add up the widths with lengths remaining the same
Re: compartor offset
Refer to the CMOS book by Jacob Baker. The comparator chapter in there nicely explains everything, including measurement techniques
This is in regards to a dc-dc converter on chip. Firstly can someone please describe the difference with regards to the above two terms. Secondly, i am thinking of designing them using comparators and resistors, is this the correct approach. Can you please help me on this. Thanks in advance...
PFD's are normally used in PLL's for comparison's...PFD's are used to provide a higher acquistion range because using just a PD puts a constraint on acquisition based on the loop filter frequency. A frequency detector can be use din conjunction with the PD in the same loop. The PLL first brings...
i assume u mean to make asynchronous counters or dividers....Use T-flip flops and external combinational logic to provide delays...look again whether u want synchronous or asynchronous...because in async case u will have to take a lot of care about delays
I'm trying to design an asynchronous counter using 6 T-flip flops. It is giving a reasonable output but of course with alot of delay. I am going to use some combinational logic for the exact divide ratio i require. I havent done it as yet,have just simulated the 6 flops feeding into each other...
I'm trying to design an asynchronous counter using 6 T-flip flops. It is giving a reasonable output but of course with alot of delay. I am going to use some combinational logic for the exact divide ratio i require. I havent done it as yet,have just simulated the 6 flops feeding into each other...
Can someone help me with what is the standard load (capacitive) normally assumed for say in ASIC library design if i'm going to make some basic gates for the above mentioned process
propagation delay and fall time in cmos inverter
It has to drive the input of a NAND gate...can i take it to be driving another inverter??...also could someone please help me with the propagation delay relationship to the rise time question i'd posted earlier and how to determine the...
ads cmos inverter design
Thank you for your reply...i think i have referred that book but am still confused...let me rephrase my question...i wanted to know how to determine the load capacitance if i'm designing the inverter as a stand alone cell cause i think once i know that and the i/p rise...
Hi all
Am a freshie and new to designing and have to design a CMOS inverter from scratch...a full custom design ..cannot use standard cells...in other words i have to design an inverter and some other logic gates and incorporate them together to form a flip flop and in turn an asynchronous...
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