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The mode pin functionality looks like a data valid signal. The user who is driving this module need not necessarily continuously drive the DIN. So whenever he drives a valid input on DIN he will drive a value of '01' of DIN.
From here things are getting a bit vague. If it were me, i would have...
Am speaking of the current code which ghostridergr has posted. It looks obvious that the variables are not meant to be registers.
Again, am speaking of the 'constants' which ghostridergr is talking of. Am asking him not to ignore anytime this warning shows up, after what i see, i understand all...
1) You need not initialize variables in reset. Reset should be used to provide initial values for signals, not variables. Hence most signals (including flag) will be called combinatorial signals even though they are not meant to be.
2) Right, your synthesizer is not able to recognize ur array...
ya the MAC frame that comes from MAC layer is mapped onto the subchannels allocated according to the modulation scheme applied. So for a particular modulation scheme if the no. of subchannels is reduced it means that the no. of bits mapped on to those sub-channels is reduced. Yes it happens...
Just look at the dimensions of the Reed-Solomon encoding scheme that is directed by the standard. U will see that when sub-channelization is applied the data becomes too small to use RS on a sub-channel basis...
Are you looking at the outputs after sufficient number of clocks? If not i guess u won't be getting the outputs because: for each module the inputs need to come after shifting from the registers, so the second module output appears a clock cycle after the first module output and similarly for...
It has been ages since i touched verilog. Can anyone help me remember if # sign can also be synthesized? I remember its used for delay like a = #1 b where it means assign b to a after 1 ns. Is that right?
I have got an RTL code now that has the # signs used in a statement a = #1 b;
Are there...
can you be more specific in your question..i have experience modelling fft/ifft for wimax transciever ... implemented both with scaling and without scaling
fft help
TRy implementing the butterfly architecture given in DSP textbooks in VHDL....clue:implement one butterfly per clock cycle...it will be an efficient design.
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