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Re: LOW POWER ASIC
My idea is:
1. If your problem is peak power :
Use some power compiler or in apr stage to distribute your logic, make
logic not to toggle at same time.
2. If your problem is average power:
You can use
2.1 Low power cell from foundry
2.2 Use design to...
Reset needs buffer trees of course because you need to initialize all internal registers' state, so the design can work after reset.
In apr tools, you jsut treat it as a high fanout net, then do the buffer tree insertion.
But you must check reset signal 's latency to each ffs.
1. Setup time violation:
Slow down your chip clock freq., if OK, then it is setup time violation.
2. If slow down still failed -> hold time violation.
But some time it is due to power problem, so, raise up or down your chip working
voltage can give you idea about failure reason.
Re: Microcontroller project
option 1. Find a simulator. Try to find execution environment on internet.
According to that environemnt's setting to do some practice.
option 2. Spend money, buy 8051 tool kit (board), according to that board's environment, write some code, upload your...
There exists some un-clear points in your description. PLease describe
your methodology. And,
What do you mean "testing"? main function or test coverage?
Roughly,
0)
Usually, we use "divide & conquer" way to verify your design. That means, you must write your golden model first in TOP...
cdl spice
If you have synopsys hercules, you can use "nettran" utility to do the transformation.
Actually, the difference between cdl and spice is small, you can write your own utility to do the conversion, I think perl is a not-bad programming language choice.
Re: PAD AND POWER RING
And, put pad power ring outside, core power ring inside.
If possible, divide the power between analog and digital parts if
your analog circuit is sensitive.
Check bus "a" 's width. If bus "a" is from bit 7 to bit 0,
Solution 1:
You need to put all of them in "@(...)" block.
Solution 2:
always @( a[0] or a[1[] )
begin
b[0] = a[0];
b[1] = a[1];
end
Solution 3:
always @( a[0] or a[1[] )
begin
b = { a[1], a[0] };
end
Some of them may be...
Yep, for pure RTL Verilog/VHDL simulation, I think VCS is trash too.
For AMDS-> only suitable for big logic and medium analog custom block.
For Adit -> under spice +rtl environment,
[Disadvantage]: compared with VCS+Nanosim, Speed poor. and for verilog syntax support is also poor too...
I don't think so. I use VCS + NANOSIM to do mixed mode simulation under "big standard logic" + "middle scale customed logic" environment. It is really great.
The most important thing is: current VCS only support VCS(master) + Nanosim(slave) cosimulation environment. But in the future, they...
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