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Recent content by abimann

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    Artix7 XC7A100T BRAM Math

    Hello, one question when we use Dual port BRAM as a interface to DDR3, A side port can be 8 bit port and B side port 128bits, and address respectively 11bits and 8bits, when FrameValid and LineValid is ON, data is available, so that time address increase to 1, and write enable is 1 when data...
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    Artix7 XC7A100T BRAM Math

    one pixel 8 bit, frame countless.
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    Artix7 XC7A100T BRAM Math

    Hello, I know it, because it saves picture in bram and shows an image through vga. Canno find in Xilinx ISE
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    Artix7 XC7A100T BRAM Math

    Hello dear gurus! In Datasheet of Artyx7 XC7A100T has 270 18KB blocks to save image frame from camera needed 9 830 400s (1280x960x8) bit but cannot make Bram IP, can save little more than 4 915 200s (1280x960x4) but 8x1024 is equal 1KB 8x1024x270 is equal 2 211 840bits So Saved 4 915...
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    Error :Syntax error near "module"

    Re: Error :Syntax error near "module" Yes, now i have a lot of time, due to the covid19. Will learn Verilog as I will print it out. one questioin is in shortest time need to be find.: is equal to VHDL folowing code ??? : - - - Updated - - - equal or not?
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    Error :Syntax error near "module"

    Yes, now i have a lot of time, due to the covid19. Will learn Verilog as I will print it out. one questioin is in shortest time need to be find.: is equal to VHDL folowing code :
  7. A

    Error :Syntax error near "module"

    it says: what is that mean, it need to assign to some register ? I plan to put data from camera , of cause that 's no constant.
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    Error :Syntax error near "module"

    Re: Error :Syntax error near "module" i create VHDL file and paste verilog code. thanks - - - Updated - - - I think , i make it working. but here is other problem, The VHDL concatenate operator is ampersand (&) and what is analogue in Verilog ? or how to do ? How to add...
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    Error :Syntax error near "module"

    I just try to compile, and it gave me ERROR.
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    Error :Syntax error near "module"

    Hello, hope everything goes well, and covid19 will stop soon.. I am very new in Verilog, use xilinx vivado 19., want to add ddr3. what a problem cannot understand.. clock wizard and mem modules done normally step by step as in instruction..code i got from...
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    explanation about bram and ddr3

    I found one code,but it even simple said in website i got it, doesnot work, led_calib is on, but led_pass not on, if even leds how "10101.." i could make counter for address and etc. I have only one chip so (no chip select). could some one tell me what problem is here ? module dram_fifo (...
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    explanation about bram and ddr3

    Hello dear Gurus and normal guys. I have a question : When i connect camera 8 bit to the Artix 7 (XC7A100T 18kb bram -270 36kb bram-135 max kb-4,860) i can use BRAM for camera 640x480x8 8bit,when framevalid and linevalid on, counter starts to work and make address,wr enabled then on camera...
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    ERROR:HDLParsers:709

    Dear all Gurus and just good guys! Pls tell me what's wrong with my code, top level file is in VHDL , lower level file is Verilog,why i get this kind of error ? I remember that VHDL and Verilog works well in my old projects and this is not reason. ERROR:HDLParsers:709 -...
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    Bayer Pattern to RGB VHDL CODE

    Somewhere i found out , that it need to use Matlab, pls could someone explain how to use Matlab exactly on this purpose ?
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    Bayer Pattern to RGB VHDL CODE

    Please VHDL Guru's i got 8 rows Bayer signal from MT9 parallel data camera , could someone help me or share VHDL code to convert from Bayer pattern to RGB ?
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