Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by abhishek.k

  1. A

    CMOS Analog Switch and the +/- 20mA current injection

    Re: CMOS Analog Switch Hi IanP, I also thought so, but the meaning of this spec is that in OFF mode, the switch shoould not start conduction when +/- 25mA of current is injected from input. However I am still not very clear on how to incorporate in my design. Can anyone help me? Regards...
  2. A

    CMOS Analog Switch and the +/- 20mA current injection

    site:www.edaboard.com cmos switch Hi All, I am desining a CMOS Analog Switch with Ron < 500 Ohms . However one specification for the Switch says that "it should be able to handle +/- 20mA current injection". What exactly does this injection current spec means, and how should I take care...
  3. A

    Which tools can be used for the ESD simulations for ASICs?

    Re: ESD TOOLS Yes !! I agree with DrProf. For Simulating Breakdown / Snapback behaviour, the foundry need to upgrade the models. Anyway, in modern designs we are usually moving towards the non-breakdown type of devices which are easy to simulate and predict
  4. A

    How to decide metal rails (or Power rails) in I/Os architect

    Re: How to decide metal rails (or Power rails) in I/Os archi 1. Metal width should be sufficient so as to avoid EM 2. Metal width should be sufficient so as to keep IR drop within specefications. 3. Metal Rails should follow ESD considerations also. Should be sufficient wide to carry the ESD...
  5. A

    I/O Pads (with ESD) - how to do it

    Re: I/O Pads (with ESD) For Analog Pad , metal rails should be such that the capacitance is minimum. Also you need to avoid the second stage resistor depending on voltage or current signal
  6. A

    ESD in PECL output buffer

    Can you give me the idea of the protection startegy which you have used, ie, What type of clamps and where you have place them
  7. A

    Which tools can be used for the ESD simulations for ASICs?

    Re: ESD TOOLS You can simulate Non breakdown devices by HBM and MM. This example is for Hspice HBM2kV simulation SUBCKT HBM NEG POS RR1 NET20 POS 1.5K LL4 NET20 NET5 7.5u CC5 POS NEG 10p IC=0 CC4 NET20 POS 1p IC=0 CC0 NET5 NEG 100p IC=2K .ENDS HBM
  8. A

    Guidelines for I/O pad simulation

    Re: I/O pad simulation Rajesh is right!! You can simulate HBM and MM events for Non breakdown clamps. For exmaple , in Hspice this works for HBM 2kV: SUBCKT HBM NEG POS RR1 NET20 POS 1.5K LL4 NET20 NET5 7.5u CC5 POS NEG 10p IC=0 CC4 NET20 POS 1p IC=0 CC0 NET5 NEG 100p IC=2K .ENDS HBM
  9. A

    Can somebody give me some advice about ESD simulation?

    Hi . Hspice can simulate only the Non breakdown type of Devices/clamp. You can simulate the responce of RC Mosfet Clamps and diodes. This is sample model for HBM 2kV Zap in Hspice. SUBCKT HBM NEG POS RR1 NET20 POS 1.5K LL4 NET20 NET5 7.5u CC5 POS NEG 10p IC=0 CC4 NET20 POS 1p IC=0 CC0 NET5...
See more

Part and Inventory Search

Back
Top