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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity viterbi_count is
port (enc_data:in std_logic_vector(1 downto 0);
dec_data:out std_logic_vector(7 downto 0);
test :out std_logic_vector(7 downto 0);
clock : in...
dont know what these macrocells are tricky... But im using epm7160slc84-10 from altera....
Barry- ya i changed and merged both the processes... after i posted it here that is(trickydicky, please make note) and changed all the signals to variables...
Any change in your replies? Thanks in advance
Says it needs 276 macrocells and 176 shareable expanders.... Can u please help me reduce these two to 160 each?
[CODE]
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use work.data_packages.all;
entity Viterbi_new is
port...
mine is altera 7160slc.... should i stick to my version or is better one preferred... please post link for the download page, and please answer my other question , "Are u talking about the simulator, i mean vector waveform file? In that case, I dop know what tht is and have tried it for the...
Are u talking about the simulator, i mean vector waveform file? In that case, I dop know what tht is and have tried it for the program... But to no avail
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Also, is it possible to get a newer version of quartus. I mean for free..... And if i do, will I get to configure a FPGA...
the following is the code i wrote afresh for the same decoding scheme.....
library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.data_packages.all;
entity Viterbi_new is
port (clock: in std_logic;
--ct: buffer integer range 0 to 16...
how do i use packages for the task... can i include all the functions i need in the same package? Also, if i write different components one after the other in the viterbi_decode WITHOUT a loop or process, will they execute iteratively (or simply,loop after completing the last component in order)...
Hey people,
I am working on viterbi decoding in vhdl. I am using altera quartusII 6.0. I am posting the code and the problem, please help me rectifyy utlibrary ieee;
library work;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use work.data_packages.all;
entity...
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